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rev 1.0 characteristics subject to change without notice. 1 of 23 256k 32k x 8 bit ft28hc256 5 volt, byte alterable eeprom features access time: 90ns simple byte and page write single 5v supply no external high voltages or v pp control circuits self-timed no erase before write no complex programming algorithms no overerase problem low power cmos active: 60ma standby: 500? software data protection protects data against system level inadvertent writes high speed page write capability highly reliable d irect write endurance: 1,000,000 cycles data retention: 100 years early end of write detection data polling toggle bit polling description the ft28hc256 is a second generation high perfor- mance 32k x 8 eeprom. block diagram x buffers latches and decoder i/o buffers and latches y buffers latches and decoder control logic and timing 256kbit eeprom array i/o 0 Ci/o 7 data inputs/outputs ce oe v cc v ss a 0 Ca 14 we address inputs the ft28hc256 supports a 128-byte page write opera- tion, effectively providing a 24s/byte write cycle, and enabling the entire memory to be typically rewritten in less than 0.8 seconds. the ft28hc256 also features data polling and toggle bit polling, two methods of providing early end of write detection. the ft28hc256 also supports the jedec standard software data pro- tection feature for protecting against inadvertent writes during power-up and power-down. endurance for the ft28hc256 is specified as a mini- mum 1,000,000 writecycles per byte and an inherent data retention of 100 years. a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 2 of 23 rev 1.0 pin configuration a 14 a 12 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v ss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v cc we a 13 a 8 a 9 a 11 oe a 10 ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 ft28hc256 plastic dip cerdip flat plastic soic a 6 a 5 a 4 a 3 a 2 a 1 a 0 nc i/o 0 a 8 a 9 a 11 nc oe a 10 ce i/o 7 i/o 6 4 3 2 1 32 31 30 14 15 16 17 18 19 20 5 6 7 8 9 10 11 12 13 29 28 27 26 25 24 23 22 21 lcc plcc a 7 i/o 1 i/o 2 v ss i/o 3 i/o 4 i/o 5 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a 3 a 4 a 5 a 6 a 7 a 12 a 14 nc v cc nc we a 13 a 8 a 9 a 11 oe 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 nc v ss nc i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 ce a 10 a 12 a 14 nc v cc we a 13 nc ft28hc256 ft28hc256 11 i/o 0 10 a 0 14 v ss 9 a 1 8 a 2 7 a 3 6 a 4 5 a 5 2 a 12 28 v cc 12 i/o 1 13 i/o 2 15 i/o 3 4 a 6 3 a 7 1 16 i/o 4 20 ce 22 oe 24 a 9 17 i/o 5 27 we 19 i/o 7 21 a 10 23 a 11 25 a 8 18 i/o 6 26 a 13 (bottom view) pga a 14 ft28hc256 tsop pin descriptions addresses (a 0 ? 14 ) the address inputs select an 8-bit memory location during a read or write operation. chip enable (ce ) the chip enable input must be low to enable all read/ write operations. when ce is high, pow er consump- tion is reduced. output enable (oe ) the output enable input controls the data output b uff- ers, and is used to initiate read oper ations. data in/data out (i/o 0 ?/o 7 ) data is wr itten to or read from the ft28hc256 through the i/o pins. write enable (we ) the write enable input controls the w riting of data to the ft28hc256. pin names symbol description a 0 Ca 14 address inputs i/o 0 Ci/o 7 data input/output we write enable ce chip enable oe output enable v cc +5v v ss ground nc no connect a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 3 of 23 rev 1.0 device operation read read operations are initiated by both oe and ce low. the read operation is term inated by either ce or oe returning high. this two line control architecture elimi- nates bus contention in a system env ironment. the data bus will be in a high impedance state when either oe or ce is high. write write oper ations are initiated when both ce and we are lo w and oe is high. the ft 28hc256 suppor ts both a ce and we or we , whiche ver occurs last. simila rl y, the data is latched internally by the rising edge of either ce or we , which ev er occurs first a byte write operation, once initiated, will automatically continue to comple- tion, typically within 3ms. page write operation the page wri te f eature of the ft28hc256 allows the entire memory to be wri tten in typically 0.8 seconds . page wr ite all ows up to one hundred twenty-eight bytes of data to be consecuti vely written to the ft 28hc256, prior to the commencement of the inter nal programming cycle . the host can fetch data from another device within the system du ring a page write operation (change the source address), but the page address (a 7 through a 14 ) f or each subsequent valid write cycle to the part during this operation must be the same as the initial page address. the page wr ite mode can be initiated dur ing any write operation. following the initial byte write cycle, the host can write an additional one to one hundred twenty- seven bytes in the same manner as the firs t b yte was written. each successi ve by te load cycle , start ed b y the we high to lo w tr ansition, m ust begin within 100s of the falling edge of the preceding we . if a sub- sequent we high to low tr ansition is not detected within 100s , the inte rnal automatic progr amming cycle will commence . there is no page w ri te windo w limitation. effectively the page write window is infinitel wide, so long as the host conti nues to access the device within the byte load cycle time of 100s. write operation status bits the ft 28hc256 provides the user two write operation status bits. these can be used to optimi sed a system write cycle time. the status bits are mapped onto the i/o bus as shown in figure 1. figure 1. status bit assignment data polling (i/o 7 ) the ft 28hc256 features d a t a polling as a method to indicate to the host system that the by te write or page write cycle has completed. d a t a polling allows a sim- ple bit test operation to determine the status of the ft 28hc256. this eliminates additional interrupt inputs or external hardware. during the internal programming cycle, any attempt to read the last byte written will pro- duce the complement of that data on i/o 7 (i.e ., wr ite data = 0xxx xxxx, read data = 1xxx xxxx). once the programming cycle is complete , i/o 7 will reflect true data. toggle bit (i/o 6 ) the ft28hc256 also provides another method for determining when the inte rn al write cycle is complete . during the inte rn al programming cycle i/o 6 will toggle from high to lo w and low to high on subsequent attempts to read the device. when the internal cycle is complete the toggling will cease, and the device will be accessible for additional read and write operations. 5tb dp 43210 i/o reserved toggle bit data polling controlled wri te cycle. that is, the address is latched b y the f alling edge of either ce a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 4 of 23 rev 1.0 data polling i/o 7 figure 2. data polling bus sequence ce oe we i/o 7 ft28hc256 ready last write high z v ol v ih a 0 Ca 14 an an an an an an v oh an figure 3. data polling software flow d a t a polling can effectively halve the time for writing to the ft 28hc256. the timing diagr am in figure 2 illus- trates the sequence of events on the bus. the software flow diag ram in figure 3 illustrates one method of implementing the routine. write data save last data and address read last address io 7 compare? ft28hc256 no yes writes complete? no yes ready a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 5 of 23 rev 1.0 the toggle bit i/o 6 figure 4. toggle bit bus sequence ce oe we last write i/o 6 high z * * v oh v ol ready * i/o 6 beginning and ending state of i/o 6 will vary. figure 5. toggle bit software flow ? the toggle bit can eliminate the chore of s aving and fetching the last address and data in order to implement d a t a polling. this can be especially helpful in an array comprised of multiple ft28hc256 memories that is frequently updated. the timing dia gr am in figure 4 illustrates the sequence of events on the bus. the soft- ware f low diagram in figure 5 illustrates a method for polling the toggle bit. hardware data protection the ft28hc256 provides two hardware features that protect nonvolatile data from inadvertent writes. C default v cc senseall write functions are inhibited when v cc is 3.5v typically. C write inhibitholding either oe low, we high, or ce high will prevent an inadvertent write cycle during power-up and power-down, maintaining data integrity. software data protection the ft 28hc256 offers a softw are-controlled data pro- tection f eature. the ft28hc256 is shipped from ft with the software data protection not enabled; that is, the device will be in the standard operating mode. in this mode data should be protected duri ng power-up/ down oper ations through the use of e xternal circuits . the host would then have open read and wr ite access of the device once v cc was stable. the ft28hc256 can be automatically protected during power-up and power-down (without the need for exter- nal circuits) by employing the software data protection feature. the inter nal software data protection circuit is enabled after the first w ite operation, utili sing the soft- ware algor ithm. this circuit is non volatile, and will remain set for the life of the device unless the reset command is issued. once the software protection is enabled, the ft28hc256 is also protected from inadvertent and accidental writes in the powered-up state. that is, the softw are algorithm must be issued prior to writing additional data to the device. compare ft28c256 no yes ok? compare accum with addr n load accum from addr n last write ready yes a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 6 of 23 rev 1.0 software algorithm selecting the software data protection mode requires the host system to precede data wri te operations by a series of three w rite operations to three specific addresses. refer to figure 6 and 7 fo r the sequence . the three-byte sequence opens the page wr ite window, enabling the host to w rite from one to one hundred twenty-eight b ytes of data. once the page load cycle has been completed, the device will automatically be returned to the data protected state. software data protection figure 6. timing sequence?yte or page write ce we (v cc ) write protected v cc 0v data address aaa 5555 55 2aaa a0 5555 t blc max writes ok byte or age t wc figure 7. write sequence for software data protection regardless of whether the de vice has previously been protected or not, once the software data protection algorithm is used and data has been w ritten, the ft28hc256 will automatically disable further writes unless another command is issued to cancel it. if no further commands are issued the ft28hc256 will be write protected du ri ng power-down and after any sub- sequent power-up. note: once initiated, the sequence of wri te operations should not be interrupted. write last write data xx to any write data a0 to address 5555 write data 55 to address 2aaa write data aa to address 5555 after t wc re-enters data protected state byte to last address address optional byte/page load operation byte/page load enabled a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 7 of 23 rev 1.0 resetting software data protection figure 8. reset software data protection timing sequence ce we standard operating mode v cc data address aaa 5555 55 2aaa 80 5555 t wc aa 5555 55 2aaa 20 5555 figure 9. write sequence for resetting software data protection in the e vent the user wa nts to deactiv ate the software data protection feature for testing or reprog ramming in an eeprom programmer, the f ollowing six step algo- rithm will reset the internal protection circuit. after t wc , the ft 28hc256 will be in standard operating mode. note: once initiated, the sequence of wri te operations should not be interrupted. system considerations because the ft28hc256 is frequently used in large memory ar ra ys, it is pr ovided with a two line control architecture for both read and w ri te operations. proper usage can pro vide the l ow est possible power dissipa- tion, and eliminate the possibility of contention where multiple i/o pins share the same b us. to gain the most benefit, it is recommended that c e be decoded from the address bus and be used as the pr i- mary de vice selection input. both oe and we would then be common among all devices in the arra y. for a read operation, this assures that all deselected devices are in their standby mode, and that only the selected device(s) is/are outputting data on the bus. because the ft28hc256 has two pow er modes , standby and activ e, proper decoupling of the memo ry array is of prime concern. enabling ce will cause tran- sient current spik es. the magnitude of these spi kes is dependent on the output capacitive loading of the l/os. therefore, the larger the arr ay sharing a common bus, the larger the transient spike s. the voltage peaks associated with the current transients can be sup- pressed by the proper selection and placement of decoupling capacitors. as a minimum, it is recommended write data 55 to address 2aaa write data 55 to address 2aaa write data 80 to address 5555 write data aa to address 5555 write data 20 to address 5555 write data aa to address 5555 after t wc , re-enters unprotected state a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 8 of 23 rev 1.0 that a 0.1f high frequency ceramic capacitor be used between v cc and v ss at each dev ice. depending on the size of the arra y, the value of the capacitor may have to be larger. in addition, it is recommended that a 4.7f electrolytic bulk capacitor be placed bet we en v cc and v ss fo r each eight de vices emplo yed in the ar ra y. this bulk capacitor is employ ed to ov ercome the voltage droop caused by the inductive effects of the pc board traces. a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 9 of 23 rev 1.o absolute maximum ratings temperature under bias ft 28hc256 ...................................... C10c to +85c ft28hc256i, ft 28hc256m............. C65c to +135c storage temperature ........................ C65c to +150c voltage on any pin with respect to v ss ........................................C1v to +7v d.c. output current ............................................. 10ma lead temperature (soldering, 10 seconds)........ 300c comment stresses above those listed under absolute maximum ratings m ay cause permanent damage to the dev ice. this is a stress ra ting only; functional operation of the device (at these or any other conditions above those indi- cated in the operational sections of this specification) i not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0c +70c industrial C40c +85c military C55c +125c supply voltage limits ft28hc256 5v 10% d.c. operating characteristics (over recommended operating conditions unless otherwise specified.) notes: (1) typical values are for t a = 25c and nominal supply voltage. (2) v il min. and v ih max. are for reference only and are not tested. power-up timing note: (3) this parameter is periodically sampled and not 100% tested. symbol parameter limits unit test conditions min. typ. (7) max. i cc v cc active current (ttl inputs) 30 60 ma ce = oe = v il , we = v ih , all i/os = open, address inputs = .4v/2.4v levels @ f = 10mhz i sb1 v cc standby current (ttl inputs) 1 2 ma ce = v ih , oe = v il , all i/os = open, other inputs = v ih i sb2 v cc standby current (cmos inputs) 200 500 a ce = v cc C 0.3v, oe = gnd, all i/os = open, other inputs = v cc C 0.3v i li input leakage current 10 a v in = v ss to v cc i lo output leakage current 10 a v out = v ss to v cc , ce = v ih v ll (2) input low voltage C1 0.8 v v ih (2) input high voltage 2 v cc + 1 v v ol output low voltage 0.4 v i ol = 6ma v oh output high voltage 2.4 v i oh = C4ma symbol parameter max. unit t pur (3) power-up to read 100 s t puw (3) power-up to write 5 ms a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 10 of 23 rev 1.0 capacitance t a = +25c, f = 1mhz, v cc = 5v endurance and data retention symbol test max. unit conditions c i/o (9) input/output capacitance 10 pf v i/o = 0v c in (9) input capacitance 6 pf v in = 0v parameter min. max. unit endurance 1,000,000 cycles data retention 100 years a.c. conditions of test mode selection equivalent a.c. load circuit symbol table input pulse levels 0v to 3v input rise and fall times 5ns input and output timing levels 1.5v ce oe we mode i/o power l l h read d out active l h l write d in active h x x standby and write inhibit high z standby x l x write inhibit x x h write inhibit 5v 1.92k ? 30pf output 1.37k ? waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low dont care: changes allowed changing: state not known n/a center line is high impedance a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 11 of 23 rev 1.0 a.c. characteristics (over the recommended operating conditions, unless otherwise specified. read cycle limits read cycle notes: (4) t lz min., t hz , t olz min. and t ohz are periodically sampled and not 100% tested, t hz and t ohz are measured with cl = 5pf, from the point when ce , oe t ce t rc address ce oe we data valid t oe t lz t olz t oh t aa t hz t ohz data i/o v ih high z data valid return high (whichever occurs first) to the time when the outputs are no longer diven. symbol parameter )7+&)7+&)7+&)7+& unit min. max. min. max. min. max. min. max. t rc (5) read cycle time 70 90 120 150 ns t ce (5) chip enable access time 70 90 120 150 ns t aa (5) address access time 70 90 120 150 ns t oe output enable access time 35 40 50 50 ns t lz (4) ce low to active output 0 0 0 0 ns t olz (4) oe low to active output 0 0 0 0 ns t hz (4) ce high to high z output 35 40 50 50 ns t ohz (4) oe high to high z output 35 40 50 50 ns t oh output hold from address change 0 0 0 0 ns a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 12 of 23 rev 1.0 write cycle limits notes: (6) typical values are for t a = 25? and nominal supply voltage. (7) t wc is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. it is the maximum time the device requires to automatically complete the internal write operation. (8) t wph and t dw are periodically sampled and not 100% tested. we controlled write cycle symbol parameter min. typ. (6) max. unit t wc (7) write cycle time 3 5 ms t as address setup time 0 ns t ah address hold time 50 ns t cs write setup time 0 ns t ch write hold time 0 ns t cw ce pulse width 50 ns t oes oe high setup time 0 ns t oeh oe high hold time 0 ns t wp we pulse width 50 ns t wph (8) we high recovery (page write only) 50 ns t dv data valid 1 s t ds data setup 50 ns t dh data hold 0 ns t dw (8) delay to next write after polling is true 10 ? t blc byte load cycle 0.15 100 ? address t as t wc t ah t oes t ds t dh t oeh ce we oe data in data out high z data valid t cs t ch t wp a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 13 of 23 rev 1.0 ce controlled write cycle page write cycle notes: (9) between successive byte writes within a page wr ite operation, oe can be strobed lo w: e.g. this can be done with ce and we high to fetch data from another memory device within the system for the next write; or with we high and ce low effectively per- forming a polling operation. (10)the timings shown above are unique to page write operations. individual byte load operations within the page write must con form to either the ce or we controlled write cycle timing. address t as t oeh t wc t ah t oes t cs t ds t dh t ch ce we oe data in data out high z data valid t cw we oe (9) last byte byte 0 byte 1 byte 2 byte n byte n+1 byte n+2 t wp t wph t blc t wc ce address (10) i/o *for each successive write within the page write operation, a 7 Ca 15 should be the same or writes to an unknown address could occur. a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 14 of 23 rev 1.0 data polling timing diagram (11) toggle bit timing diagram (11) note: (11)polling operations are by definition read cycles and are thereore subject to read cycle timings. address a n d in = x t wc t oeh t oes ce we oe i/o 7 t dw a n a n d out = x d out = x ce oe we i/o 6 t oes t dw t wc t oeh high z * * * i/o 6 beginning and ending state will vary, depending upon actual t wc . a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 15 of 23 rev 1. 0 packaging information 28-lead ceramic flat pack type f note: all dimensions in inches (in parentheses in millimeters) 0.740 (18.80) max. 0.019 (0.48) 0.015 (0.38) 0.050 (1.27) bsc 0.045 (1.14) max. pin 1 index 128 0.130 (3.30) 0.090 (2.29) 0.045 (1.14) 0.025 (0.66) 0.180 (4.57) min. 0.006 (0.15) 0.003 (0.08) 0.030 (0.76) min. 0.370 (9.40) 0.250 (6.35) typ. 0.300 2 plcs. 0.440 (11.18) max. a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 16 of 23 rev 1.0 packaging information 0.561 (14.25) 0.541 (13.75) 28-lead ceramic pin grid array package type k note: all dimensions in inches (in parentheses in millimeters) 0.020 (0.51) 0.016 (0.41) 12 13 15 17 18 11 10 14 16 19 9 8 20 21 7 6 22 23 5 2 28 24 25 4 3 1 27 26 typ. 0.100 (2.54) all leads 0.080 (2.03) 4 corners 0.070 (1.78) pin 1 index 0.660 (16.76) 0.640 (16.26) 0.110 (2.79) 0.090 (2.29) 0.072 (1.83) 0.062 (1.57) 0.185 (4.70) 0.175 (4.44) 0.050 (1.27) 0.008 (0.20) a a a a note: leads 4,12,18 & 26 0.080 (2.03) 0.070 (1.78) a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 17 of 23 rev 1.0 packaging information note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.022 (0.56) 0.014 (0.36) 0.160 (4.06) 0.120 (3.05) 0.625 (15.88) 0.590 (14.99) 0.110 (2.79) 0.090 (2.29) 1.470 (37.34) 1.400 (35.56) 1.300 (33.02) ref. pin 1 index 0.160 (4.06) 0.125 (3.17) 0.030 (0.76) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.040 (1.02) 0.557 (14.15) 0.510 (12.95) 0.085 (2.16) 0.040 (1.02) 0 15 28-lead plastic dual in-line package type p typ. 0.010 (0.25) a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 18 of 23 rev 1.0 packaging information 28-lead plastic small outline gull wing package type s 0.299 (7.59) 0.290 (7.37) 0.419 (10.64) 0.394 (10.01) 0.020 (0.508) 0.014 (0.356) 0.0200 (0.5080) 0.0100 (0.2540) 0.050 (1.270) bsc 0.713 (18.11) 0.697 (17.70) 0.012 (0.30) 0.003 (0.08) 0.105 (2.67) 0.092 (2.34) x 45 notes: 1. all dimensions in inches (in parentheses in millimeters) 2. formed lead shall be planar with respect to one another within 0.004 inches seating plane base plane 0.42" max. 0.030" typical 28 places 0.050" typical 0.050" typical footprint 0.0350 (0.8890) 0.0160 (0.4064) 0.013 (0.32) 0.008 (0.20) 0 C 8 a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 19 of 23 rev 1.0 packaging informatin 0.620 (15.75) 0.590 (14.99) typ. 0.614 (15.60) 0.110 (2.79) 0.090 (2.29) typ. 0.100 (2.54) 1.690 (42.95) max. 0.023 (0.58) 0.014 (0.36) typ. 0.018 (0.46) 0.232 (5.90) max. 0.060 (1.52) 0.015 (0.38) pin 1 0.200 (5.08) 0.125 (3.18) 0.065 (1.65) 0.033 (0.84) typ. 0.055 (1.40) 0.610 (15.49) 0.500 (12.70) 0.100 (2.54) max. 0 15 32-lead hermetic dual in-line package type d note: all dimensions in inches (in parentheses in millimeters) 0.005 (0.13) min. 0.150 (3.81) min. 0.015 (0.38) 0.008 (0.20) seating plane a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 20 of 23 rev 1.0 packaging information 0.150 (3.81) bsc 0.458 (11.63) CC 0.458 (11.63) 0.442 (11.22) pin 1 0.020 (0.51) x 45 ref. 0.095 (2.41) 0.075 (1.91) 0.022 (0.56) 0.006 (0.15) 0.055 (1.39) 0.045 (1.14) typ. (4) plcs. 0.040 (1.02) x 45 ref. typ. (3) plcs. 0.050 (1.27) bsc 0.028 (0.71) 0.022 (0.56) (32) plcs. 0.200 (5.08) bsc 0.558 (14.17) CC 0.088 (2.24) 0.050 (1.27) 0.120 (3.05) 0.060 (1.52) pin 1 index corner 32-pad ceramic leadless chip carrier package type e note: 1. all dimensions in inches (in parentheses in millimeters) 2. tolerance: ?% nlt ?.005 (0.127) 0.300 (7.62) bsc 0.015 (0.38) min. 0.400 (10.16) bsc 0.560 (14.22) 0.540 (13.71) dia. 0.015 (0.38) 0.003 (0.08) a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 21 of 23 rev 1.0 packaging information 0.021 (0.53) 0.013 (0.33) 0.420 (10.67) 0.050 (1.27) typ. typ. 0.017 (0.43) 0.045 (1.14) x 45 0.300 (7.62) ref. 0.453 (11.51) 0.447 (11.35) typ. 0.450 (11.43) 0.495 (12.57) 0.485 (12.32) typ. 0.490 (12.45) pin 1 0.400 (10.16) ref. 0.553 (14.05) 0.547 (13.89) typ. 0.550 (13.97) 0.595 (15.11) 0.585 (14.86) typ. 0.590 (14.99) 3 typ. 0.048 (1.22) 0.042 (1.07) 0.140 (3.56) 0.100 (2.45) typ. 0.136 (3.45) 0.095 (2.41) 0.060 (1.52) 0.015 (0.38) seating plane 0.004 lead co C planarity 32-lead plastic leaded chip carrier package type j notes: 1. all dimensions in inches (in parentheses in millimeters) 2. dimensions with no tolerance for reference only 0.510" typical 0.050" typical 0.050" typical 0.300" ref. foo tprint 0.400" 0.410" 0.030" typical 32 places a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 22 of 23 rev 1.0 packaging information 8.02 (0.315) 7.98 (0.314) 1.18 (0.046) 1.02 (0.040) 0.17 (0.007) 0.03 (0.001) 0.26 (0.010) 0.14 (0.006) 0.50 (0.0197) bsc 0.58 (0.023) 0.42 (0.017) 14.15 (0.557) 13.83 (0.544) 12.50 (0.492) 12.30 (0.484) pin #1 ident. o 0.76 (0.03) seating plane see note 2 see note 2 0.50 0.04 (0.0197 0.0016) 0.30 0.05 (0.012 0.002) 14.80 0.05 (0.583 0.002) 1.30 0.05 (0.051 0.002) 0.17 (0.007) 0.03 (0.001) typical 32 places 15 eq. spc. 0.50 0.04 0.0197 0.016 = 7.50 0.06 (0.295 0.0024) overall tol. non-cumulative solder pads footprint note: 1. all dimensions are shown in millimeters (inches in parentheses). 32-lead thin small outline package (tsop) type t a ll data sheet.com
ft28hc256 characteristics subject to change without notice. 23 of 23 device access time C70 = 70ns C90 = 90ns C12 = 120ns C15 = 150ns temperature range blank = commercial = 0c to +70c i = industrial = C40c to +85c m = military = C55c to +125c mb = mil-std-883 m5004 package p = 28-lead plastic dip d = 28-lead cerdip j = 32-lead plcc s = 28-lead plastic soic e = 32-pad lcc k = 28-pin grid array f = 28-lead flat pack t = 32-lead tsop ft28hc256 x x -x rev 1.0 a ll data sheet.com

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